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Description

Synthesijer is a high-level synthesis tool, which generates VHDL and Verilog HDL code from Java code. Synthesijer also provides a backend to generate VHDL/Verilog HDL, which helps to develop high-level synthesis tools and DSLs.

** Quick start** Prepare a Java program, such as,

/* Test.java */ public class Test{ public boolean flag; private int count = 0;

   public void run(){
       while(true){
           count++;
           if(count == 5000000){
               count = 0;
               flag = !flag;
           }
       }
   }

}

and compile it with Synthesijer.

synthesijer --vhdl --verilog Test.java

You can get Test.vhd and Test.v from Test.java.